At least one nanopore in NNi Conditioning Buffer
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Every solid-state nanopore in unique in some way. It is both a blessing and a curse of nanopore science. On the one hand, the quirks of nanopores and nanopore systems are often the catalyst for discoveries , while on the other hand the heterogeneity between pores can occasionally be a frustrating source of difficulty in reproducibility of experimental work. One of the many ways that NNi is working to accelerate nanopore research is to help address this variability in nanopore performance by developing tools, protocols, workflows, and experimental materials that are designed to enhance consistency and reproducibility.
Different batches of membranes produce nanopores of varying qualities [2, 3]. While there is variation between pores from a single wafer, variation is generally much larger between wafers in terms of pore stability and low-frequency noise. While the noise can often be addressed through membrane cleanliness as discussed previously, pore stability is more complex and difficult to address after the fact. The best way to mitigate these issues is to use membranes purchased from NNi, of which a subset from each batch is tested for quality pore production before any are sold.
Nanopore size measurement has historically been done by directly imaging the nanopore in a TEM. While this is certainly possible for pores made by controlled breakdown [4,5], it is less informative than you would expect. As previously discussed in the Nanopore Basics section, the cleaning and wetting procedures required to move a pore from a TEM to an aqueous environment or vice versa are likely to change the pore geometry, meaning that any size estimated this way should be taken with a grain of salt. The best way to assess nanopore geometry is to do it electrically, in the same setup in which you plan to do your biomolecular sensing. This ensures that you have up to the minute accuracy on your pore size.
Measuring pore size electrically involves measuring the electrical resistance of the pore with an I-V curve, and optionally refining your estimate using the blockages caused by a well-known molecule like double-stranded DNA translocating the pore. Detailed instructions on how to best do that are provided here, and this is routinely done for you as part of the automation involved in using NNi’s nanopore fabrication tools and software. Once you have your measurements done, simply enter them into the NNi Pore Size Calculator to get geometric details.
Under the hood, this method of measuring nanopore size makes the assumption that the nanopore can be modeled as a simple network of resistors and capacitors (an RC circuit). In the image below, we show the two main resistivity contributions to the overall electrical resistance of the nanopore: R, the bulk resistance of the pore, and r, the access resistance, with an instantaneous switch to toggle between the open pore state and the blocked state. This is a significant oversimplification of what is really happening in the pore, which is still a very active subject of research, but it suffices to gain a conceptual understanding of how electrical pore sizing works.
The most widely accepted model  of the relationship between nanopore size and electrical resistance works generally as follows. The conductance (reciprocal of resistance) of the pore itself is just modeled as a cylinder with electrical conductivity corresponding to the electrolyte solution inside, that is,
where d is the pore diameter, s is the solution conductivity, and L is the pore length. The second term relates to the fact that the solution leading up to the pore has finite conductivity, and so there is some resistance in the solution around the pore which is usually called access resistance This term is given by a resistance in series with the bulk resistance, and in reality represents the sum of the equal contribution of the access resistance on both sides of the pore.
There is in fact a third term, which is usually neglected. This resistance appears in parallel to the bulk resistance G in equation 1, and is given by
where x and y are the electrical mobility of charges counterions that congregate near the pore walls and y is the surface charge density on the nanopore.This term represents the fact that because the pore is charged, ions of opposite charge tend to cluster near the pore walls and shield it, resulting in what is called electrophoretic current. This term is usually neglected in the literature, partly because in high salt concentrations the surface contributions are shielded and become less important, and partly because if we are being honest, it's really difficult to estimate accurately. Experimental evidence shows that this approach works very well for pores in high salt concentrations when the surface charges are well-shielded .
All this, combined using your standard resistor network rules, finally brings us to the equation for pore conductance that is employed by the majority of researchers in the field as well as NNi's calculators:
Experimental evidence shows that this approach works very well for pores in high salt concentrations when the surface charges are well-shielded. You can improve the estimate further by using a molecular ruler like double-stranded DNA to measure the pore length. On the assumption that the blockage caused by DNA comes primarily from excluding a cylinder of conductive solution equal in size to the DNA inside the bulk term of the nanopore, you can measure the pore size by measuring the conductance blockage caused by the molecule, via the equation
Calculating L from equation 5 and feeding that value back into equation 4 will give the best estimate of nanopore size in highly concentrated salt solution. Or you could just use the NNi Pore Size Calculator, which even estimates the error bars for you.
The success of a nanopore experiment is usually dictated by the noise performance of the pore itself. A detailed workflow covering the measurement of nanopore noise is presented here. Once you have completed the measurement and are looking at the power spectrum of your nanopore, there are several components to the electrical noise of a nanopore to understand, shown in this obtuse equation below :
Where S(f) is the power spectrum (the squared magnitude of the Fourier transform of the open-pore current as a function of frequency f), I is the average open-pore current, kT is the Boltzmann temperature, R is the nanopore bulk resistance, r is the nanopore access resistance, D is the dielectric loss constant of the membrane, C is the chip capacitance, v is the RMS voltage noise at the input, and a, b, c, and d are prefactors that set the relative strength of each contribution, which vary between nanopores and chip architectures. Don’t worry, it’s not as ugly as it looks. The figure below breaks it down for you.
The first term of the equation is the most important in assessing nanopore quality. The 1/f noise term dominates the low-frequency regime, and is caused by an enormous variety of physical phenomena . In the figure, it's highlight in green. This term is the reason we strongly encourage piranha cleaning prior to nanopore fabrication, because a hydrophobic membrane can lead to nanobubbles on the surface, which in turn translate to large 1/f noise contributions to the power spectrum . Even though this part of the spectrum contributes relatively little to the overall noise at high bandwidth, it is the primary determinant of whether a nanopore will be able to see biomolecules at all. It is often the case that a pore with a large 1/f component will simply not allow the passage of biomolecules.
1/f noise is easily assessed using the NNi Nanopore Fabrication Hardware, following the protocol outlines in this post. The metric we use for pore quality is the L-value defined in our Nature Protocols publication. Essentially, this is the integral of the power spectrum from 1 to 100 Hz, normalized to remove the effect of pore geometry . A value below indicates a pore that will probably be useful for translocation experiments, assuming it is appropriately sized for the target as previously discussed. Note, too, that a slope other than -1 can be indicative of pore problems requiring troubleshooting as well.
If your pore exhibits 1/f noise that is too high or low-frequency noise that does not appear to be of 1/f type, the first thing to do is always to look at the current trace used to generate the power spectrum and make sure that it doesn't have any transient issues that might cause an artefact in your spectrum. Assuming there are none, there are a few options. One is to simply wait. Pores left sitting overnight in NNi Conditioning Buffer often improve their noise characteristics, at small risk of some enlargement of the nanopore . Alternatively, one can simply enlarge the nanopore further. We have seen that a 1/f noise pore can often be turned into a useful pore at a larger pore size, making this the best option for applications where a range of pore sizes is tolerable. Usually, though, the best cure is prevention, and cleaning the membrane prior to pore fabrication is the single best way to ensure success .
The second term Equation 1 is thermal noise. At room temperature and small pores this term is utterly negligible, but can become important for larger pores. If it is relevant it will appear as a flat frequency contribution in the yellow region, but it rarely matters, and there is not much optimization to be had here.
The third term is dielectric noise, in orange in the figure, and depends on the support structure of the chip and its capacitance, scaling linearly with frequency. This is quickly dominated by the capacitance fourth term in the equation in red, which scales quadratically with frequency and are the dominant contribution to the total RMS noise of the nanopore. This part of the power spectrum has little to do with the pore itself is usually highly consistent between chips, meaning that any optimization in the high-frequency regime needs to happen at the chip design level. For this purpose, NNi sells a line of chips with a layer of SiO2 separating the silicon support chip from the membrane, which serves to greatly reduce chip capacitance. If your application requires even better noise performance than is provided by NNi’s low-capacitance chip line, reach out to discuss, and we will help design a chip that can support your stringent noise requirements.
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Last Updated: 2021-05-11